Challenges in integrated circuit (IC) design continue to grow as IC technologies progress towards smaller feature sizes, such as 32 nanometers, 28 nanometers, 20 nanometers, and below. For example, when fabricating IC devices, device performance may be seriously influenced by lithography printability, which indicates how well a final wafer feature formed on a wafer corresponds with a target pattern defined by an IC design layout. Various methods that focus on optimizing a mask used for projecting an image that corresponds with the target pattern on the wafer have been introduced for enhancing lithography printability, such as optical proximity correction (OPC), mask proximity correction (MPC), inverse lithography technology (ILT), and source mask optimization (SMO). Although such methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.